Digital clock signals are commonly used in digital integrated circuits. It is important in order to ensure proper operation of digital integrated circuitry that the clock signal be present and clean. If the clock signal is not present, this is referred to by those skilled in the art as a loss of clock (LOC). A clock signal may not be clean in situations where there is a clock glitch such as with an incorrect timing of a clock edge. Detection of the loss of clock or the occurrence of a clock glitch, generally referred to herein as a clock error, is important in triggering the performance of certain actions by the digital integrated circuitry. For example, in response to the detection of a clock error, the digital circuitry may shut down, enter sleep mode, perform a reset, return to an operating state prior to the clock error detection, generate an error signal output, or perform some other operation.
There is a need in the art for clock error detection circuitry capable of detecting both loss of clock and clock glitch error. The circuitry disclosed herein addresses that need.
In this regard, a clock glitch error generally refers to an error wherein the time period of the clock is shorter than a minimum time period for which the circuits driven by the clock can work accurately, and a loss of clock generally refers to an error wherein the clock stops or experiences a clock period that is longer than a clock timing requirement.